1. Technical Field of the Invention
The present invention relates to the field of integrated circuits, and more particularly to electrically programmable three-dimensional (3-D) memory-based IC self-test.
2. Related Arts
In a three-dimensional (3-D) integrated circuit (3D-IC), one or more 3D-IC layers are stacked one above another on top of a substrate. Each IC layer comprises functional blocks such as logic, memory and analog blocks. It is typically comprised of non-single-crystalline (poly, microcrystalline or amorphous) semiconductor material. Because logic and analog blocks are sensitive to defects and non-single-crystalline semiconductor material has a large defect density, the 3D-IC comprising logic and/or analog blocks have a low yield. Moreover, logic and/or analog blocks consume large power. The three-dimension integration of these blocks faces many heat-dissipation issues. On the other hand, a memory block is less sensitive to defects because the defect-induced errors can be corrected (by, for example, redundancy circuit). Moreover, it consumes little power. Accordingly, memory is better suited for the 3-D integration.
In a three-dimensional memory (3D-M), one or more memory levels are stacked one above another on top of a substrate. As illustrated in FIG. 1, the two physical memory levels 100, 200 of the 3D-M 0 are stacked one by one on a substrate 0s. On each memory level 100, there are a plurality of address-select lines (including word line 20a and bit line 30a) and 3D-M cells (1aa . . . ). Substrate 0s comprises a plurality of transistors. Contact vias (20av, 30av . . . ) provide electrical connection between address-select lines (20a, 30a . . . ) and the substrate circuit.
The 3D-M can be categorized through the means employed to alter its contents. If the contents can be altered using electrical means, this 3D-M is an electrically programmable 3D-M (EP-3DM); if the contents are altered using non-electrical means, then this 3D-M is a non-electrically programmable 3D-M (NEP-3DM).
The electrically programmable 3D-M (EP-3DM) can be further categorized into 3-D RAM (3D-RAM), 3-D write-once memory (a.k.a. 3-D one-time programmable, i.e. 3D-OTP), and 3-D write-many (3D-WM). The 3D-RAM cell is similar to a conventional RAM cell except that the transistors used therein are thin-film transistors (TFT) 1t (FIG. 1B). The 3D-OTP cell may comprise a 3D-ROM layer 22 (e.g. a diode layer) and an antifuse layer 22a (FIG. 1C). The integrity of the antifuse layer 22a indicates the logic state of the 3D-OTP cell. The 3D-WM includes 3D-flash, 3D-MRAM (3-D magneto-resistive-material-based RAM), 3D-FRAM (3-D Ferroelectric-material-based RAM), 3D-OUM (3-D Ovonyx-unified-memory), etc. It may comprise active devices such as TFT 1t (FIGS. 1DA-1DB). The TFT-based 3D-WM may comprise a floating gate 30fg (FIG. 1DA) or a vertical channel 25c (FIG. 1DB).
An exemplary non-electrically programmable 3D-M (NEP-3DM) is mask-programmable 3-D read-only memory (3D-MPROM). It represents logic xe2x80x9c1xe2x80x9d with the existence of an info-via 24 (i.e. absence of dielectric 26) (FIG. 1EA); and logic xe2x80x9c0xe2x80x9d with the absence of an info-via (i.e. existence of dielectric 26) (FIG. 1EB). Similar to 3D-OTP cell (FIG. 1C), it also comprises a 3D-ROM layer 22 (e.g. a diode layer).
3D-M can also be categorized as conventional semiconductor memory, i.e. it can be categorized into 3D-RAM and 3D-ROM (including 3D-MPROM, 3D-OTP, 3D-WM). This is the approach used by prior patents and patent applications filed by the same inventor (U.S. Pat. No. 5,835,396, U.S. patent application Ser. No. 10/230,648, etc.) In this application, both categorizations are used interchangeably.
With low-cost, high density and large bandwidth, the 3D-M has a strong competitive edge. However, because it is typically based on non-single-crystalline semiconductor, the performance of the 3D-M cell cannot yet compete with the conventional memory. For the 3D-M designed and manufactured in conventional approaches, its performance, such as read-write speed, unit-array capacity, intrinsic yield and programmability, needs further improvement.
The present invention provides an improved three-dimensional memory (3D-M). It has better integratibility, speed, density/cost and programmability. The 3D-M can be used to form three-dimensional integrated memory (3DiM), e.g. computer-on-a-chip (ConC) and player-on-a-chip (PonC). ConC/PonC offers excellent data security. Another 3D-M application of great importance is in the area of the integrated-circuit (IC) testing. 3D-M carrying the IC test data can be integrated with the circuit-under-test (CUT), thus enabling at-speed test and self-test.
It should be noted that, although various types of the 3D-M (including both EP-3DM- and NEP-3DM) are described hereinafter, the scope of this Application is limited to the EP-3DM only. The NEP-3DM is expressly excluded from the scope of this Application.
It is a principle object of the present invention to provide an integrated circuit (IC) with self-test and at-speed test capabilities.
It is a further object of the present invention to provide an IC self-test based on electrically programmable three-dimensional memory (EP-3DM).
It is a further object of the present invention to provide an IC self-test method with minimum impact to the layout of the circuit-under-test.
In accordance with these and other objects of the present invention, an EP-3DM-based IC self-test is disclosed.
Compared with conventional memory, one greatest advantage of the 3D-M is its integratibility. Because its memory cells do not occupy substrate, most substrate real estate can be used to build complex substrate integrated circuits (substrate-IC). The substrate-IC may comprise conventional memory block, processing unit, analog block and others. 3D-M SoC (system-on-a-chip) formed from the integration between the 3D-M and substrate-IC is referred in the present invention as three-dimensional integrated memory (3DiM). The 3DiM can further improve the data security, speed, yield and software upgradibility of the 3D-M.
In a 3DiM, the substrate-IC may comprise an embedded read-write memory (eRWM) and/or an embedded processor (eP). The performance of the 3D-M and the eRWM are complementary to each other: 3D-M excels in integratibility and density/cost; RWM is better in speed and programmability. The integration of the 3D-M and the RWM combines their individual strength and can achieve an optimized system performance. On the other hand, the integration of the 3D-M and the eP can enable the on-chip processing of the 3D-M data (data stored in the 3D-M), thus improving the 3D-M data security.
One exemplary eRWM is embedded RAM (eRAM). The eRAM has a small latency. It can be used as a cache for the 3D-M data, i.e. it keeps a copy of the 3D-M data. When the eP seeks data, it searches first in the eRAM. If not found, it will then search the 3D-M. This approach reconciles the speed difference between the eP and the 3D-M. Another exemplary eRWM is embedded ROM (eROM). In general, eROM comprises non-volatile memory (NVM). The excellent programmability of the eROM can remedy the limited programmability of the 3D-M. Accordingly, the eROM is an ideal storage device for the correctional data (data used to correct defect-induced errors) and upgrade code of the 3D-M.
Computer-on-a-chip (ConC) is realized by integrating a 3D-M with an eP and an eRWM. It can perform many task of a today""s computer. One exemplary ConC is player-on-a-chip (PonC). PonC can store and play contents, including audio/video (A/V) materials, electronic books, electronic maps and others. It provides excellent copyright protection to these contents. For the conventional content-storage technologies such as optical discs, pirates can easily steal the original contents by monitoring the output signal from the content carrier (i.e. the medium that carries the content, including optical discs ROM chips and others) or by reverse-engineering the content carrier. In a PonC, the 3D-M is integrated with a content player (preferably with an on-chip D/A converter). Its output is analog (A/V) signal and/or decoded (A/V) signal. Accordingly, the original contents do not appear anywhere outside the PonC and therefore, cannot be digitally duplicated. Thus, excellent copyright protection can be achieved.
For a 3DiM using a mask-programmable 3D-M to store data (e.g. contents, codes), the data represented by the info-vias in the 3D-M are preferably encrypted. In addition, 3DiM preferably comprises an on-chip decryption engine. This on-chip decryption engine decrypts the 3D-M data. The decrypted data are directly sent to the other functional blocks on the 3DiM. For this type of the 3DiM, it is very difficult to reverse-engineer the chip using means such as de-layering.
The present invention provides means for improving the 3D-M integratibility, both from a structural perspective and from a design perspective. From a structural perspective, simple 3D-M cell is preferred. To be more specific, the diode-based 3D-ROM, particularly 3D-MPORM, is the first-choice candidate. Moreover, if the 3D-M process requires relatively high temperature, the interconnect system for the substrate circuit is preferably made of refractory conductors (e.g. refractory metal) and thermally-stable dielectrics (e.g. silicon oxide, silicon nitride). Furthermore, there are preferably a plurality of gaps between certain address-select lines in the 3D-M array. With their help, embedded wires can pass through the 3D-M array and provide interface for the substrate-IC. In addition, for the high-speed substrate-IC, a shielding layer is preferably formed between at least a portion of the 3D-M layer and the substrate circuit.
From a design perspective, unit array (i.e. the basic memory array in a chip) preferably has large capacity. This can minimize the number of unit arrays on a 3D-M chip and therefore, minimize the effect of the 3D-M""s peripheral circuits on the layout of the substrate-IC. Moreover, simple 3D-M peripheral circuit is preferred. Simple peripheral circuit occupies less substrate real estate. Accordingly, the saved space can be used to accommodate more powerful substrate-IC. Since 3D-MPROM does not need programming circuitry, it is advantageous over 3D-EPROM in this aspect. For the xe2x80x9cwrite-oncexe2x80x9d 3D-EPROM, since its programming capability is not used xe2x80x9cvery oftenxe2x80x9d, the programming voltage can be directly fed into the chip, rather than being generated on-chip.
With outstanding manufacturability and integratibility, 3D-MPROM is a very promising 3D-M. The present invention provides several self-aligned 3D-MPROM. In a self-aligned 3D-MPROM, the 3D-ROM layer is self-aligned with the word and bit lines and its formation does not require any individual pattern-transfer step. The 3D-ROM layer may be pillar-shaped, with one dimension equal to the word-line width and the other dimension equal to the bit-line width; or be a natural junction, which is naturally formed at the cross-point between the word and bit lines. Furthermore, interleaved memory levels can be used to further increase memory density. In a 3D-M with interleaved memory levels, two adjacent memory levels share one address-select line. In general, 3D-MPROM can use an nF-opening mask to define the 3D-M data. On an nF-opening mask, the opening dimension is n times (preferably, nxcx9c2) the minimum dimension supported by this technology. It has a much lower mask cost.
Compared with conventional memory, the 3D-M is typically slower. This issue can be addressed both from a design perspective and from a system perspective. From a design perspective, techniques such as sense amplifier (S/A), full-read mode and self-timing are preferably used. With an S/A, the bit-line voltage swing required to trigger a logic output is small (xcx9c100 mV), thus it takes less time to charge up the bit line and the latency is shortened. In the full-read mode, all data on a single word line are read out at the same time and therefore, the bandwidth is improved. Self-timing ensures data-validity and saves power. For programmable 3D-M, parallel programming improves the write speed.
From a system perspective, 3DiM is preferably used to hide the 3D-M latency. The eRAM in the 3DiM works as a cache for the 3D-M. After read, the 3D-M data latched at the S/A are copied into the eRAM word-by-word. When an external circuit seeks data from the 3DiM, it reads from the eRAM first. If there is a hit, the data is read out from the eRAM; otherwise the data is read out from the 3D-M. Although the performance of a single 3D-M cell cannot yet compete with the conventional memory, collectively, its system performance can match that of the conventional memory, even excel.
To improve its integratibility, 3D-M preferably has a large unit-array capacity. This can be achieved in several approaches. First of all, since NBL (NBL is the number of bit lines in a unit array) is not constrained, a unit array can be designed into a rectangular shape, i.e. NBL greater than NWL (NWL is the number of word lines in a unit array). Secondly, since NWL is constrained by the rectification ratio xcex3 of the 3D-ROM cell during read, xcex3 preferably has a large value. One xcex3-enhancement technique uses a large read voltage VR. With the usage of S/A, the reverse and forward biases in xcex3 is decoupled: the largest reverse bias is just around the threshold voltage VT of the S/A (xcx9c100 mV); whereas, the forward bias is controlled by VR, which can be separately adjusted by design. In general, the forward bias (e.g. xcx9c3V) is far greater than the reverse bias (e.g. xcx9c0.3V). Apparently, xcex3 can be improved by using larger VR. Another xcex3-enhancement technique uses polarized 3D-ROM cell. In a polarized cell, the base materials in its upper and lower layers are different, or, it has different interfaces with its top and bottom electrodes.
To improve yield, a seamless 3D-ROM cell is preferably used to lower the intrinsic defects in a 3D-ROM array. In a seamless 3D-ROM cell, all defect-sensitive layers (i.e. 3D-ROM layer and at least the portion of the bottom and top electrodes adjacent to it), are formed in a seamless way, i.e. there is no pattern-transfer step between the formations of these layers. Alternatively, error-correction schemes such as error-correction code (ECC) and redundancy circuits can be used to correct the defect-induced errors. For ECC, Hamming code is preferably incorporated in the 3D-M array. For redundancy circuits, the eROM therein preferably stores the addresses and correctional data for defects. Redundancy circuits can correct word-line errors, bit-line errors and single-bit errors. The correctional process can be carried out right after the column decoder (correction-during-read), or, in the eRAM (correction-after-read).
Besides correcting word-line errors, the word-line redundancy block provides software upgradibility for the 3D-M. In the area of software upgrade, the word-line redundancy block is also referred to as flexible-code block. Software upgrade can also use address-translation. For address-translation, the 3D-M and the eROM form a unified memory space: the 3D-M stores the original code and the eROM stores the upgrade code. The substrate-IC further comprises an address-translation block. It treats all input addresses as virtual address and translates them into the physical address for the unified memory space. If the data refer to the original code, the physical address points to the 3D-M; if the data refer to the upgrade code, the physical address points to the eROM.
Another 3D-M application of great importance is IC-testing. For the conventional testing methodology, it is difficult to achieve at-speed test and field self-test. Moreover, conventional testers are expensive. With the advent of 3D-M, particularly 3D-ROM, these issues can be addressed. The 3D-M carrying test data is preferably integrated with the circuit-under-test (CUT). During test, input test vector is first downloaded from the 3D-M to the CUT; then the output from the CUT is compared with the expected test vector. Accordingly, the CUT performance can be examined. This 3D-M-based self-test (3DMST) has many advantages: 1. With 3-D integration, the bandwidth between the CUT and the 3D-M is large. This large bandwidth can enable at-speed test to high-speed IC; 2. 3DMST can enable field self-test and self-diagnosis, thus improving the system reliability; 3. Being low-cost, the 3D-M adds little extra cost to the CUT; 4. The 3D-M has little impact to the CUT layout; 5. With a large capacity, the test data in the 3D-M can provide excellent fault coverage to the CUT.
Test vectors can be downloaded from the 3D-M to the CUT in a serial or parallel fashion. During serial downloading, test vectors are shifted one-by-one into the scan chain, during parallel downloading, test vectors are shifted into the scan chain in parallel. The integrated circuits with 3DMST capability (i.e. 3DMST-IC) can also support techniques such as parallel self-test, mixed-signal testing, and printed-circuit board (PCB) system self-test. Moreover, to reduce the amount of test data to be carried by the 3D-M, techniques such as test-data compression and composite test are preferably used. In a composite test, the 3DMST is combined with other testing techniques such as BIST and external scan test. Composite test further lowers the testing cost and improves the test reliability.
During the 3DMST, if the output test vector (OTV) mismatches the expected test vector (ETV), there are two possibilities: one is the CUT is defective; the other is the 3D-M is defective. The second scenario can cause undesired yield loss. To avoid it, methodologies such as 3DMST-with-confidence and/or secondary test are preferably followed. The 3DMST-with-confidence guarantees that the 3D-M is error-free: if there are defect-induced errors, they are corrected before the 3DMST. For the part that fails the 3DMST, a secondary test, i.e. an external scan test (EST), can be performed. Still failing the EST test, it will then be treated as a bad part. This testing methodology is also referred to as dual testing. To reduce the EST test time, the questionable test vectors (QTV, i.e. the test vectors corresponding to the mismatched OTV and ETV) are recorded during the 3DMST. Then the secondary test is only performed to the QTV.